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Logic decomposition for programmable gate arrays

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3 Author(s)
T. Luba ; Inst. of Telecommun., Warsaw Univ. of Technol., Poland ; M. Markowski ; B. Zbierzchowski

In this paper an effective decomposition algorithm for mapping of logic functions onto FPGAs is proposed. The algorithm exploits the symbolic decomposition concept to find FPGA based implementation with a minimal number of CLBs. Experimental results of the presented method are provided and compared to other similar tools

Published in:

Euro ASIC '92, Proceedings.

Date of Conference:

1-5 Jun 1992