System Maintenance:
There may be intermittent impact on performance while updates are in progress. We apologize for the inconvenience.
By Topic

ASIC and board design of a high performance parallel architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)

The integrated design of ASIC and board is a key approach for high performance parallel architectures. This paper describes the solutions adopted in the design of a parallel architecture for research purposes. The heart of the architecture is an ASIC processor (100 K transistors, 180 pin PGA, 30 MHz) with RISC features and instruction-level parallelism capabilities. The whole system design has been carried on within an integrated CAD framework, which has allowed a concurrent development of software (compiler), hardware (system board) and VLSI (processor) components. In particular, the authors present the aspects related to the design of the system board (3 ASICs, memory and ISA bus interface for a total of about 247 ICs and 8 interconnection layers), showing how different levels of board simulation can help to improve the quality of the design. They also detail the adopted pipelined design style, which shows some peculiarities with respect to traditional approaches

Published in:

Euro ASIC '92, Proceedings.

Date of Conference:

1-5 Jun 1992