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A CMOS ASIC to implement the TC sublayer in the physical layer of the ATM network

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2 Author(s)
J. Bulone ; SGS-Thomson Microelectron., Grenoble, France ; M. Diaz Nava

The line terminator (LT) is designed to support the transmission convergence (TC) sublayer in the physical layer of the ATM network. It provides high speed data communication; CCITT bit rates of 622.08 Mbit/s and 155.52 Mbit/s are supported. The LT chip has a standard microprocessor interface for ATM components. The transmit and receive sections of the LT chip are independent and can operate simultaneously

Published in:

Euro ASIC '92, Proceedings.

Date of Conference:

1-5 Jun 1992