By Topic

A CMOS ASIC to implement the TC sublayer in the physical layer of the ATM network

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Bulone, J. ; SGS-Thomson Microelectron., Grenoble, France ; Diaz Nava, M.

The line terminator (LT) is designed to support the transmission convergence (TC) sublayer in the physical layer of the ATM network. It provides high speed data communication; CCITT bit rates of 622.08 Mbit/s and 155.52 Mbit/s are supported. The LT chip has a standard microprocessor interface for ATM components. The transmit and receive sections of the LT chip are independent and can operate simultaneously

Published in:

Euro ASIC '92, Proceedings.

Date of Conference:

1-5 Jun 1992