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Delay fault models and test generation for random logic sequential circuits

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3 Author(s)
T. J. Chakraborty ; AT&T Bell Lab., Princeton, NJ, USA ; V. D. Agrawal ; M. L. Bushnell

The authors study the problem of delay fault modeling and test generation for any random logic sequential circuit. The proposed test generation method, based on transition and hazard states of signals, is applicable to any sequential circuit of either non-scan, scan or scan-hold type of design. Three fault models based on different initial state assumptions during the propagation of the fault effect to a primary output are proposed and analyzed using the proposed delay fault test generation method. A novel thirteen-value algebra is considered to simplify the analysis of robust and nonrobust tests during fault simulation of path delay faults

Published in:

Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE

Date of Conference:

8-12 Jun 1992