Distributed design-space exploration for high-level synthesis systems

A parallel algorithm for design-space exploration and trade-off analysis is presented. Coarse-grained parallelism is introduced by generating multiple module bags and performing scheduling and performance analysis of the data flow graph for each module bag in parallel. This algorithm was implemented on a multiple processor machine as part of a distributed high-level synthesis system. Experimental results showed reduction in search time, improvement in design quality, and close-to-linear speedup.<
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