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An integrated approach to realistic worst-case design optimization of MOS analog circuits

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2 Author(s)
Dharchoudhury, A. ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Kang, S.M.

The authors present a new integrated approach for the optimization of MOS analog circuit performance by using realistic worst-case device parameter files, each corresponding to a performance measure. Nonlinear response surfaces are constructed for the performance measures of interest, and the worst-case device parameter files are identified by solving a set of suitably cast nonlinear programming problems. The worst-case files are shown to depend on the values of the designable parameters. An efficient method of incorporating this dependence during worst-case design optimization has been developed. This method enables the design of circuits with optimal performance and high parametric yields. Some illustrative analog circuit examples are given to demonstrate the application of the worst-case design optimization procedure

Published in:

Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE

Date of Conference:

8-12 Jun 1992