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Performance evaluation of latency tolerant architectures

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4 Author(s)
Nemawarkar, S.S. ; Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada ; Govindarajan, R. ; Gao, G.R. ; Agarwal, V.K.

The authors analyze a single processor multithreaded architecture using stochastic timed Petri net (STPN) model to study the effects of various parameters such as memory latency and thread runlength, on processor utilization. They first perform a simple analysis of the basic model with constant values for the parameters. This is followed by an extension with stochastic parameters. A detailed simulation study is conducted to validate the analysis. While earlier researchers established that an increase in the number of threads results in increased processor utilization, their results, on the other hand, indicate that average runlength and effective memory latency have stronger impact on processor utilization than the number of threads

Published in:

Computing and Information, 1992. Proceedings. ICCI '92., Fourth International Conference on

Date of Conference:

28-30 May 1992