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Pattern matching and parallel processing with CCD technology

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4 Author(s)
Pedroni, V.A. ; California Inst. of Technol., Pasadena, CA, USA ; Agranat, A. ; Neugebauer, C. ; Yariv, A.

A fully parallel charge coupled device (CCD) memory chip of N address lines is presented. It detects, in just one clock cycle, a perfect matching between input pattern and any of the stored patterns. It detects in fewer than N cycles the best matching in case a perfect one does not exist. The charge packets, representing binary words, are generated by external pulses that are applied to the chip through data input lines and then are compared to the data applied to the address lines. The chip architecture is described. This chip is suitable for applications in pattern recognition, Kanerva memories, data decoders, and other systems that require peak detection or Hamming distance calculation. Typical results expected in these kinds of implementations based on similar devices are reported

Published in:

Neural Networks, 1992. IJCNN., International Joint Conference on  (Volume:3 )

Date of Conference:

7-11 Jun 1992