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A data compression technique for built-in self-test

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3 Author(s)
S. M. Reddy ; Dept of Electr. & Comput. Eng., Iowa Univ., IA, USA ; K. K. Saluja ; M. G. Karpovsky

A data compression technique called self-testable and error-propagating space compression is proposed and analyzed. Faults in a realization of Exclusive-OR and Exclusive-NOR gates are analyzed, and the use of these gates in the design of self-testing and error propagating space compressors is discussed. It is argued that the proposed data-compression technique reduce the hardware complexity in built-in self-test (BIST) logic designs using external tester environments

Published in:

IEEE Transactions on Computers  (Volume:37 ,  Issue: 9 )