Decimation filter compiler for oversampling A/D applications

A silicon compiler (DECGEN) which generates a decimation filter for oversampling A/D converters is described. It generates a multistage filter consisting of two stages of sinc filter and an equiripple bandshaping FIR filter. A heuristic procedure is derived for dividing the decimation ratio between the two stages of sinc filter in an optimum fashion. Digit serialization and hardware multiplexing are used for the target architecture in order to reduce silicon area.<
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