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Design of self-checking iterative networks

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2 Author(s)
Dhawan, S. ; IBM, Austin, TX, USA ; De Vries, R.C.

The relevant definitions are given and a model of self-checking iterative network is presented. A general combinational circuit was developed that is totally self-checking and can detect an error on the input code lines and transmit the error to the output code lines. Thus, an error generated in a cell is transmitted from cell to cell until the last cell is reached. The error, and fault that generated it, can be detected by the checker at the last cell, which can also be made self-checking. The added redundancy increases the amount of logic required to realize the circuit, and the increase depends on the circuit being realized. If z is the number of output code lines for a general cell, a rough estimate of the percent increase in circuitry is 1/z×100

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Computers, IEEE Transactions on  (Volume:37 ,  Issue: 9 )