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A 3-D sidewall flash EPROM cell and memory array

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2 Author(s)
H. Pein ; Philips Lab., Briarcliff Manor, NY, USA ; J. D. Plummer

A new 3-D sidewall flash EPROM cell has been implemented in a novel memory array. The sidewall cell is a single-transistor stacked gate cell built on the sidewalls of a silicon pillar. The gates surround the pillar and current flows vertically from top to bottom of the pillar. The cell size approaches the square of the minimum pitch and is less than 40% of that of the conventional NOR-type structure. The cell and array architecture promise to be highly scalable.<>

Published in:

IEEE Electron Device Letters  (Volume:14 ,  Issue: 8 )