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Bipolar CMOS-merged technology for a high-speed 1-Mbit DRAM

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6 Author(s)
Y. Kobayashi ; Hitachi Ltd., Ibaraki, Japan ; K. Asayama ; M. Oohhayashi ; R. Hori
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A novel high-performance bipolar-CMOS (complementary metal oxide semiconductor) merged technology for a 1-Mb DRAM (dynamic random access memory) is proposed. A memory cell having a twenty-times-higher soft-error immunity (as compared to the conventional device) in its bit-line mode and a bipolar transistor having a high-drive ability (fT=5.2 GHz at Ic=1.2 mA) can be realized. The fabrication process is fully compatible with the conventional CMOS DRAM and involves only three additional masking steps. An experimental 1-Mb BiCMOS (bipolar CMOS) DRAM was fabricated using this technology, with a typical access time of 32 ns

Published in:

IEEE Transactions on Electron Devices  (Volume:36 ,  Issue: 4 )