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Formal verification of fail-safeness of a comparator for redundant system using regular temporal logic

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2 Author(s)
K. Kawakubo ; Fac. of Eng., Fukuyama Univ., Hiroshima, Japan ; H. Hiraishi

The authors propose a method of formal verification of fault-tolerance of sequential machines using regular temporal logic. In this method, fault-tolerant properties are described in the form of input-output sequences in regular temporal logic formulas and they are formally verified by checking if they hold for all possible input-output sequences of the machine. The authors illustrate the method of its application for formal verification of fail-safeness with an example of a comparator for redundant system. The result of verification shows effectiveness of the proposed method

Published in:

Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)

Date of Conference:

26-27 Nov 1992