By Topic

A test application scheme for embedded full-scan circuits to reduce testing costs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Pomeranz, I. ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; Reddy, S.M.

The authors present a method to reduce test storage and test application time for stored-pattern testing in embedded full-scan circuits, without compromising the fault coverage. A combination of stored-pattern and built-in test is proposed to reduce the test storage and test application time by shifting output patterns back to the inputs of the circuit (similar to circular BIST), using the output responses of the circuit as additional test patterns. The circuit operates in such an autonomous mode as long as new faults can be detected. Externally applied, or stored, patterns are used to initialize the autonomous test application phase to maximize the fault coverage each phase achieves, and minimize the number of phases required

Published in:

Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)

Date of Conference:

26-27 Nov 1992