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A 64-GHz fT and 3.6-V BVCEO Si bipolar transistor using in situ phosphorus-doped and large-grained polysilicon emitter contacts

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7 Author(s)
Nanba, M. ; Hitachi Ltd., Gunma, Japan ; Uchino, T. ; Kondo, M. ; Nakamura, T.
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A high-performance bipolar transistor has been developed using an in-situ phosphorus doped polysilicon (IDP) technique for emitter formation. The transistor demonstrated in ultrahigh current gain of 700, a maximum cutoff frequency fT(max) of 64 GHz, and a breakdown voltage between collector and emitter BVCEO of 3.6 V. At VCE values of 2 and 3 V, a product of fT(max) and BVCEO of 200 GHz-V has been achieved. This value is nearly equal to the physical limitation for homojunction silicon transistors

Published in:

Electron Devices, IEEE Transactions on  (Volume:40 ,  Issue: 8 )

Date of Publication:

Aug 1993

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