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Memory requirements to balance thus asymptotically full-speedup FFT computation on processor arrays

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1 Author(s)
Shieh, J.-C. ; Aero Ind. Dev. Center, Taichung, Taiwan

The paper proves that for a linearly-connected array of α processors or a mesh-connected array of α2 processors, where each processor has computation bandwidth C, I/O bandwidth I and C/I=logm, Ω(mα) memory size is required in each processor to minimize the I/O requirement in balancing the FFT computation. Then it presents balanced FFT algorithms on these arrays to meet their memory size lower bounds. These algorithms are time optimal exhibiting full speedups

Published in:

Parallel Processing Symposium, 1992. Proceedings., Sixth International

Date of Conference:

23-26 Mar 1992

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