Cart (Loading....) | Create Account
Close category search window

Memory requirements to balance thus asymptotically full-speedup FFT computation on processor arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Shieh, J.-C. ; Aero Ind. Dev. Center, Taichung, Taiwan

The paper proves that for a linearly-connected array of α processors or a mesh-connected array of α2 processors, where each processor has computation bandwidth C, I/O bandwidth I and C/I=logm, Ω(mα) memory size is required in each processor to minimize the I/O requirement in balancing the FFT computation. Then it presents balanced FFT algorithms on these arrays to meet their memory size lower bounds. These algorithms are time optimal exhibiting full speedups

Published in:

Parallel Processing Symposium, 1992. Proceedings., Sixth International

Date of Conference:

23-26 Mar 1992

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.