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Communication performance in multiple-bus systems

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2 Author(s)
Q. Yang ; Dept. of Electr. Eng., Toronto Univ., Ont., Canada ; S. G. Zaky

A simple queueing model is presented for studying the effect of multiple-bus interconnection networks on the performance of asynchronous multiprocessor systems. The proposed model is suitable for systems in which each processor has a local memory and is thus able to continue processing while waiting for a response from the global memory. An approximate, closed-form solution is given that is simple and easy to use for any number of processors, buses, or memory modules and for arbitrary memory block size. The model is used to study the access time of the global memory as a function of the number of buses for different local-memory/global-memory traffic rates

Published in:

IEEE Transactions on Computers  (Volume:37 ,  Issue: 7 )