Time domain algorithms and architectures for Reed-Solomon decoding

Reed-Solomon decoders can be designed using time or frequency domain algorithms. The main advantage of the time domain method is its regular computational structure, an attractive feature for a flexible VLSI implementation. The main disadvantage of this is the relatively high computation count, hence it is important to find a means of reducing the computational complexity of the time domain method. Several modifications to the time domain Reed-Solomon decoding algorithm are described for reducing its computational complexity by about 60%, as well as regular VLSI architectures for implementing the time domain algorithm. The paper concludes with a discussion of the advantages and disadvantages of the time domain decoding technique.<>