By Topic

A synthesis algorithm for reconfigurable interconnection networks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Insup Lee ; Dept. of Comput. & Inf. Sci., Pennsylvania Univ., Philadelphia, PA, USA ; Smitley, D.

The performance of a parallel algorithm depends in part on the interconnection topology of the target parallel system. An interconnection network is called reconfigurable if its topology can be changed between different algorithm executions. Since communication patterns vary from one parallel algorithm to another, a reconfigurable network can effectively support algorithms with different communication requirements. It is shown how to generate a network topology that is optimized with respect to the communication patterns of a given task. The algorithm presented takes as input a task graph and generates as output a topology that closely matches the given input graph. The topologies generated by the algorithm are analyzed with respect to optimum interconnection topologies for the best, worst, and average cases. Simulation results verify the average-case performance prediction and confirm that, on the average, the optimum topologies are generated

Published in:

Computers, IEEE Transactions on  (Volume:37 ,  Issue: 6 )