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C-17A mission computer built-in test and fault management strategies

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1 Author(s)
Sinaki, G. ; Delco Systems Operations, Goleta, CA, USA

The author summarizes the C-17A mission computer (MC) built-in test (BIT) and fault management strategies. The MC is designed to be a highly reliable and fail-safe computer to prevent inadvertent display of hazardously misleading information (HMI) on the head-up and head-down displays. The MC/EDS (electronic display subsystem) probability of HMI is required not to exceed 10-9 per one hour of operation. In order to guarantee this, the MC subsystem uses triple modular redundancy and voting schemes to detect the failures and isolate them to a line replaceable unit (LRU). Extensive internal BIT and monitoring schemes are used to enhance the fault-detection and isolation capabilities of a single MC. The MC, as the bus controller on the Mission Bus (MIL-STD-1553B), is also responsible for in-flight fault detection, fault reporting, and fault recording of the mission BUS LRUs. In order to accomplish this, the MC periodically gathers fault information from all the mission Bus LRUs. The MC in-flight fault detection, reporting, and recording strategies are presented. The MC/EDS on-ground maintenance strategy is discussed, the MC internal BIT modes such as power-up, periodic, and initiated BIT are reviewed

Published in:

Aerospace and Electronics Conference, 1992. NAECON 1992., Proceedings of the IEEE 1992 National

Date of Conference:

18-22 May 1992