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A reconfiguration scheme for yield enhancement of large area binary tree architectures

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2 Author(s)
M. C. Howells ; Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada ; V. K. Agarwal

A reconfiguration scheme is presented that is suitable for both yield and reliability enhancement of large-area VLSI implementations of binary tree architectures. The approach proposed makes use of partially global redundancy to allow clustered effects to be tolerated. The binary tree is cut a few levels above the leaves to form an upper subtree and many lower subtrees, with spare processors being grouped adjacent to the root of each lower subtree. Redundant links with programmable switches are used to permit reconfiguration. The cost of the scheme, in terms of redundant hardware, is comparable to that of other schemes. An O(N ) H-tree layout is used. In comparison to existing schemes, the proposed scheme gives much better yield and better reliability

Published in:

IEEE Transactions on Computers  (Volume:37 ,  Issue: 4 )