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Hierarchical scheduling of DSP programs onto multiprocessors for maximum throughput

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2 Author(s)
Hoang, P. ; Dept. of Electr. Eng., California Univ., Berkeley, CA, USA ; Rabaey, J.

A multiprocessor scheduling algorithm that simultaneously considers pipelining, retiming, parallel execution and hierarchical node decomposition to maximize performance throughput is presented. The algorithm is able to take into account interprocessor communication delays, and memory and processor availability constraints. The results on a set of benchmarks demonstrate the algorithm's ability to achieve near optimal speedups across a wide range of applications of various types of concurrency, with good scalability with respect to processor count

Published in:

Application Specific Array Processors, 1992. Proceedings of the International Conference on

Date of Conference:

4-7 Aug 1992