By Topic

High-speed VLSI architectures for soft-output Viterbi decoding

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Joeressen, O. ; RWTH Aachen, Germany ; Vaupel, M. ; Meyr, H.

During the last few years decoding algorithms that make not only the use of soft quantized inputs but also deliver soft decision outputs have attracted considerable attention because additional coding gains are obtainable in concatenated systems. A prominent member of this class of algorithms is the soft-output viterbi algorithm. In this paper two architectures for high speed VLSI implementations of the soft-output viterbi-algorithm are proposed and area estimates are given for both architectures. The well known trade-off between computational complexity and storage requirements is played to obtain new VLSI architectures with increased implementation efficiency. Area savings in excess of 40% in comparison to straightforward solutions are reported

Published in:

Application Specific Array Processors, 1992. Proceedings of the International Conference on

Date of Conference:

4-7 Aug 1992