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Logic verification algorithms and their parallel implementation

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4 Author(s)
H. -K. T. Ma ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; S. Devadas ; Ruey-Sing Wei ; A. Sangiovanni-Vincentelli

LOgic VERification (LOVER) incorporates a novel approach to combinational logic verification and obtains excellent results when compared to existing techniques. The authors describe a new verification algorithm, LOVER-PODEM, whose enumeration phase is based on PODEM. A variant of LOVER-PODEM, called PLOVER, is presented. Parallel logic verification schemes have been developed for the first time. Issues in efficiently parallelizing both general and specific LOVER-based approaches to logic verification over a large number of processors are addressed. The parallelism inherent in the LOVER framework regardless of what enumeration and simulation algorithms are used is discussed. Since the enumeration phase is the efficiency bottleneck in parallelizing LOVER-based approaches, parallel versions of PODEM-based enumeration algorithms have been developed

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:8 ,  Issue: 2 )