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Analysis of distributed resistance effects in MOS transistors

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5 Author(s)
J. Horan ; Analog Devices BV, Limerick, Ireland ; C. Lyden ; A. Mathewson ; C. G. Cahill
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A method of modeling the distributed source and drain resistance effects in MOS transistors is discussed. Simulations performed using this technique are validated by comparisons with purpose-built structures. The method is then used to examine a problem which arises with the use of a high-temperature interconnect in three-dimensional silicon-on-insulator technologies. The results show how the resistivity of the interconnect affects the performance of the substrate devices of this technology, and the benefits achievable through further development of the existing interconnect technologies are outlined. Finally, the procedure is used to examine the effect of reduced contact size on standard MOS devices, and results wh1ich give general guidelines to the extent of the effect are presented

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:8 ,  Issue: 1 )