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Scheduling of DSP programs onto multiprocessors for maximum throughput

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2 Author(s)
P. D. Hoang ; Dept. of Electr. Eng., California Univ., Berkeley, CA, USA ; J. M. Rabaey

A flow graph scheduling algorithm that simultaneously considers pipelining, retiming, parallelism, and hierarchical node decomposition is presented. The ability to simultaneously consider the many types of concurrency allows the scheduler to find efficient multiprocessor solutions for a wide range of DSP applications. It has been implemented as part of a software environment for scheduling DSP programs onto fixed and configurable multiprocessor systems. The results on a set of benchmarks demonstrate that the algorithm achieves near ideal speedups even across programs with different types of concurrency

Published in:

IEEE Transactions on Signal Processing  (Volume:41 ,  Issue: 6 )