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A programmable analog VLSI neural network processor for communication receivers

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3 Author(s)
J. Choi ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; S. H. Bang ; B. J. Sheu

An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require prior estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mm×6.8 mm and was fabricated in a 2-μm double-polysilicon CMOS technology. System analysis and experimental results are presented

Published in:

IEEE Transactions on Neural Networks  (Volume:4 ,  Issue: 3 )