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Switch-level timing verification for CMOS circuits: a semianalytic approach

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2 Author(s)
Yang, H.G. ; Dept. of Eng., Cambridge Univ., UK ; Holburn, D.M.

The authors describe a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation

Published in:

Circuits, Devices and Systems, IEE Proceedings G  (Volume:137 ,  Issue: 6 )

Date of Publication:

Dec 1990

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