Efficient systolic high speed architectures for delayed multipath two-dimensional FIR and IIR digital filtering

Two novel efficient block-level systolic architectures for the high speed realisation of delayed multipath two-dimensional FIR and IIR digital filters are presented. With the new transformation method presented, an extra loop delay is allowed in the recursive part of the multipath structure of an IIR digital filter. Two methods for the stabilisation of the transformation method are also introduced. The resultant block-level systolic structures remove the global communication requirements, which further increases the efficiency of the final realisation