By Topic

Computation of prime factor DFT and DHT/DCCT algorithms using cyclic and skew-cyclic bit-serial semisystolic IC convolvers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Gudvangen, S. ; Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK ; Holt, A.G.J.

The authors present the results of a study of the use of cyclic and skew-cyclic convolvers for the evaluation of the subspace discrete Fourier transforms (DFT) and discrete Hartley transform (DHT) modules resulting from a prime factor decomposition of the DFT and the DHT/discrete cas-cas transform (DCCT), respectively. The method of Rader (1968) is employed to convert the subspace DFT/DHT modules into cyclic convolutions (CCs). These are further dissected into CCs and skew-cyclic convolutions (SCCs), respectively, of length 1/2(NI-1), where Ni is the DFT/DHT module length in the ith stage. That allows both real and complex DFT modules, as well as DHT modules, to be computed with the same convolver structure, by a simple reconfiguration of a recombination stage. A family of VLSI building block processors (BBPs) with pipelined bit-serial arithmetic is proposed. All inner products are computed in parallel within each BBP, resulting in a throughput rate inversely proportional to 1/2(Ni+1)

Published in:

Circuits, Devices and Systems, IEE Proceedings G  (Volume:137 ,  Issue: 5 )