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Design of one-dimensional systolic-array systems for linear state equations

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2 Author(s)
Jen, C.-W. ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Jou, S.-J.

To solve linear state equations, a two-dimensional systolic-array system has been proposed. For the same purpose, various kinds of one-dimensional arrays have been designed and discussed by the authors. The linear systolic-array system with first-in-first-out (FIFO) queues can be designed by applying double projections from the three-dimensional dependence graph (DG). As the array thus designed needs processors with multifunction operations and various input/output requirements, tag control bits are incorporated, and so make the overall computation more efficient. Furthermore, a linear systolic-array system with content addressable memory (CAM) is designed which can use the advantage of matrix sparseness to reduce the overall computation time. A partition scheme for the linear systolic-array system is also proposed to match the limitation of the pin number and the chip area. Finally, the cost and performance of all the class of systolic-array systems for solving linear state equations are illustrated

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Circuits, Devices and Systems, IEE Proceedings G  (Volume:137 ,  Issue: 3 )