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Sparcle: an evolutionary processor design for large-scale multiprocessors

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7 Author(s)
Agarwal, A. ; Lab. for Comput. Sci., MIT, Cambridge, MA, USA ; Kubiatowicz, J. ; Kranz, D. ; Lim, B.H.
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The design of the Sparcle chip, which incorporates mechanisms required for massively parallel systems in a Sparc RISC core, is described. Coupled with a communications and memory management chip (CMMU) Sparcle allows a fast, 14-cycle context switch, an 8-cycle user-level message send, and fine-grain full/empty-bit synchronization. Sparcle's fine-grain computation, memory latency tolerance, and efficient message interface are discussed. The implementation of Sparcle as a CPU for the Alewife machine is described.<>

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Micro, IEEE  (Volume:13 ,  Issue: 3 )