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Random pattern testability of delay faults

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2 Author(s)
Savir, J. ; IBM, Poughkeepsie, NY, USA ; McAnney, W.H.

In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. Here, the capability of random patterns to detect slow paths in combinational logic is analyzed. Formulas that relate the length of the test to the desired test quality are derived

Published in:

Computers, IEEE Transactions on  (Volume:37 ,  Issue: 3 )