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Application of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technology

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6 Author(s)
Bafleur, M. ; Lab. d''Autum. et d''Anal. des Syst., CNRS, Toulouse, France ; Buxo, J. ; Vidal, M.P. ; Givelin, P.
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An original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology is presented. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up

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Electron Devices, IEEE Transactions on  (Volume:40 ,  Issue: 7 )