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A single chip parallel multiplier by MOS technology

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2 Author(s)
Nakamura, S. ; Thayer Sch. of Eng., Dartmouth Coll., Hanover, NH, USA ; Chu, K.-Y.

A parallel multiplier design based on the five-counter cell is discussed. A design optimization for the performance in speed is proposed at the logic design level which is developed into an MOS circuit design. The comparison of the five-counter cell design and the full adder cell design reveals that the proposed design is most useful with pass gate logic and results in high-speed multiplication (approximately twice as fast as that of the full adder design) with a moderate increase in hardware complexity. With the five-counter design, an improvement in the hardware complexity of a squarer can be expected

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Computers, IEEE Transactions on  (Volume:37 ,  Issue: 3 )