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A new systolic realization for the discrete Fourier transform

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2 Author(s)
D. C. Kar ; Dept. of Electr. Eng., North Dakota State Univ., Fargo, ND, USA ; V. V. B. Rao

A systolic array for the discrete Fourier transform (DFT) is proposed. In comparison with previous schemes, the proposed scheme reduces the number of multipliers required almost by half and thus saves a considerable amount of hardware

Published in:

IEEE Transactions on Signal Processing  (Volume:41 ,  Issue: 5 )