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High-speed addition in CMOS

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2 Author(s)
Quach, N.T. ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; Flynn, M.

A fully static complementary metal-oxide semiconductor (CMOS) implementation of a Ling-type 32-bit adder is described. The implementation saves up to one gate delay and always reduces the number of serial transistors in the worst-case critical path over the conventional carry look-ahead (CLA) approach with a negligible increaser in hardware

Published in:

Computers, IEEE Transactions on  (Volume:41 ,  Issue: 12 )