By Topic

On fault tolerance of reconfigurable arrays using spare processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Sugihara, K. ; Dept. of Inf. & Comput. Sci., Hawaii Univ., Manoa, Honolulu, HI, USA ; Kikuno, T.

Addresses fault tolerance of a processor array that is reconfigurable by replacing faulty processors with spare processors. The fault tolerance of such a reconfigurable processor array depends on not only an algorithm for spare processor assignment but also an organization of spare processors in the reconfigurable array. The paper discusses a relationship between fault tolerance of reconfigurable arrays and their organizations of spare processors with respect to the smallest number of faulty processors for which the reconfigurable array cannot be failure-free as a processor array system no matter what reconfiguration is used. An optimum n×n reconfigurable array using 2n spare processors is presented

Published in:

Fault Tolerant Systems, 1991. Proceedings., Pacific Rim International Symposium on

Date of Conference:

26-27 Sep 1991