An approach to optimal DFT using partial parallel scan

Because traditional scan design techniques such as LSSD, scan path, and random access scan suffer from the drawback that the extra test application effort is quite significant, the partial parallel scan technique has been presented. This new technique reduces test application effort by 1 or 2 orders of magnitude. A way to get a circuit design which best improves testability greatly by using the partial parallel scan technique is discussed. Some useful algorithms are given for optimal design