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Reduced voltage swing, high speed CMOS driver, receiver techniques for multiple chip set applications

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1 Author(s)
Ta, P.D. ; VLSI Technol. Inc., San Jose, CA, USA

A 1.0 mu m CMOS reduced voltage swing driver and receiver capable of driving 30 pF at minimum frequency of 200 MHz, while cutting power consumption by a factor of 14 compared with standard CMOS circuits is described. The drivers do not require extra power supply and external resistors and are suitable for broadband ASIC multi-chip set design.<>

Published in:

Euro ASIC '91

Date of Conference:

27-31 May 1991