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A good input ordering for circuit verification based on binary decision diagrams

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2 Author(s)
Saucier, G. ; Inst. Nat. Polytech. de Grenoble, France ; Poirot, F.

Verification methods for standard cell logic are based on binary decision diagrams (BDD) comparison. The reference Boolean equations as well as the network of standard cell logic are represented by ordered BDDs (OBDDs). The main issue is to find a good input ordering to reduce both the number of nodes in the BDDs and the computation time needed to construct as well as to compare them.<>

Published in:

Euro ASIC '91

Date of Conference:

27-31 May 1991