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A tutorial on built-in self-test. 2. Applications

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3 Author(s)
Agrawal, V.D. ; AT&T Bell Lab., Murray Hill, NJ, USA ; Kime, C.R. ; Saluja, K.K.

For pt.1 see ibid., vol.10, no.1, p.73-82 (1993). The hardware structures and tools used to implement built-in self-test (BIST) pattern generation and response analysis concepts are reviewed. The authors describe testing approaches for general and structured logic, including ROMs, RAMs, and PLAs. They illustrate BIST techniques with real-world examples.<>

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Design & Test of Computers, IEEE  (Volume:10 ,  Issue: 2 )