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Fault-tolerant array processors using single-track switches

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3 Author(s)
S. -Y. Kung ; Dept. of Electr. Eng., Princeton Univ., NJ, USA ; S. -N. Jean ; C. -W. Chang

An array grid model based on single-track switches is proposed. A reconfigurability theorem is developed to provide the theoretical footing for novel reconfiguration algorithms for the fabrication-time and run-time processing. For fabrication-time yield enhancement, the problem of finding a feasible reconfiguration using global control can be reformulated as a maximum independent set problem. An existing algorithm in graph theory is adopted to solve this problem. The simulations conducted indicate that the algorithm is computationally very efficient; therefore, it may also be applicable to certain run-time fault tolerance. In real-time fault tolerance, the propagation time of data/control signals between the host computer incurred in the global control is often prohibitively long; therefore, only distributed processing is feasible. Based on the same reconfigurability theorem, a distributive reconfiguration algorithm is developed for (asynchronous) array processors

Published in:

IEEE Transactions on Computers  (Volume:38 ,  Issue: 4 )