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Circuit reliability of memory cells with SEU protection [for space application]

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1 Author(s)
J. E. Vinson ; Harris Semiconductor, Melbourne, FL, USA

The use of high value polysilicon resistors to provide SEU (single event upset) hardening introduces a latent failure mechanism when not properly tested. This failure mechanism is only present in parts with SEU resistors. The resistance prevents detection of gate oxide defects using normal test techniques. As the circuit ages, the defect becomes more conductive, resulting in a functional failure. A detailed description of the failure mechanism and a set of distinguishing characteristics to aid in failure analysis are provided. Screening the defect population requires a simple high-voltage data retention test. The use of this screen reduced the failure rate in the subject circuit by over 30×

Published in:

IEEE Transactions on Nuclear Science  (Volume:39 ,  Issue: 6 )