By Topic

Circuit reliability of memory cells with SEU protection [for space application]

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Vinson, J.E. ; Harris Semiconductor, Melbourne, FL, USA

The use of high value polysilicon resistors to provide SEU (single event upset) hardening introduces a latent failure mechanism when not properly tested. This failure mechanism is only present in parts with SEU resistors. The resistance prevents detection of gate oxide defects using normal test techniques. As the circuit ages, the defect becomes more conductive, resulting in a functional failure. A detailed description of the failure mechanism and a set of distinguishing characteristics to aid in failure analysis are provided. Screening the defect population requires a simple high-voltage data retention test. The use of this screen reduced the failure rate in the subject circuit by over 30×

Published in:

Nuclear Science, IEEE Transactions on  (Volume:39 ,  Issue: 6 )