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On mapping algorithms to linear and fault-tolerant systolic arrays

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2 Author(s)
V. K. P. Kumar ; Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA ; Y. -C. Tsai

A simple mapping technique is developed to design systolic arrays with limited I/O capability. The technique is used to improve systolic algorithms for some matrix computations on linearly connected arrays of PEs (processor elements) with constant I/O bandwidth. The important features of these designs are modularity with constant hardware in each PE, few control lines, simple data-input/output format, and improved delay time. This technique is extended to design an optimal nn-time systolic algorithm for n×n matrix multiplication with O(√n) I/O bandwidth requirement on a fault-tolerant VLSI model. In this model, the propagation delay is assumed to be proportional to wire length. Fault reconfiguration is achieved by using buffers to bypass faulty PEs, which does not affect the clock rate of the system. The unidirectional flow of control and data assures correctness of the algorithm in the presence of faulty PEs. The design can be implemented on reconfigurable fault-tolerant VLSI arrays using the Diogenes methodology. The present designs are compared to those in the literature and are shown to be superior with respect to I/O format, control, and delay from input to output

Published in:

IEEE Transactions on Computers  (Volume:38 ,  Issue: 3 )