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Fast parallel algorithms for binary multiplication and their implementation on systolic architectures

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2 Author(s)
Sinha, B.P. ; Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA ; Srimani, P.K.

Two algorithms for parallel multiplication of two n-bit binary numbers are presented. Both use column compression to increase the speed of execution. They require almost regular interconnection between only two types of cells and hence are very suitable for VLSI implementation. Both of them can also be easily modified to handle two's complement numbers with constant differences in time

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Computers, IEEE Transactions on  (Volume:38 ,  Issue: 3 )