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Neuron MOS binary-logic integrated circuits. II. Simplifying techniques of circuit configuration and their practical applications

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2 Author(s)
T. Shibata ; Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan ; T. Ohmi

For pt.I see ibid., vol.40, no.3, p.570-6 (March 1993). The fundamental circuit ideas developed by the authors in Part I are applied to practical circuits, and the impact of neuron MOSFET on the implementation of binary-logic circuits is examined. For this purpose, two techniques are presented to simplify the circuit configurations. It is shown that the input-stage D/A converter circuit in the basic configuration can be eliminated without any major problems, resulting in improved noise margins and speed performance. Then a design technique for symmetric functions, which is especially important when the number of input variables increases, is presented. The νMOS logic design is characterized by a large reduction in the number of transistors as well as of interconnections. However, the decrease in transistor count comes at a cost in process tolerance due to the multivalued nature of the device operation. Test circuits were fabricated by a typical double-polysilicon CMOS process, and the measurement results are presented

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IEEE Transactions on Electron Devices  (Volume:40 ,  Issue: 5 )