By Topic

Predictive worst case statistical modeling of 0.8-μm BICMOS bipolar transistors: a methodology based on process and mixed device/circuit level simulators

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
I. C. Kizilyalli ; AT&T Bell Lab., Allentown, PA, USA ; T. E. Ham ; K. Singhal ; J. W. Kearney
more authors

The authors discuss the use of mixed-level physics-based device/circuit simulation software and semiconductor process simulator in the construction of predictive worst case process conditions for bipolar transistors currently being manufactured in AT&T 0.8-μm BICMOS technology. Process fluctuations are introduced into the process simulator using the Latin hypercube (Monte Carlo) sampling method. The method is different from those in previous similar studies in that the compact device model parameter extraction step for each sample process is bypassed and active devices in the circuit are described by the physical device simulator rather than a compact model representation. This eliminates deficiencies associated with compact semiconductor device models. Furthermore, inaccuracies and difficulties introduced by compact model parameter extractions (especially for bipolar transistors) are also eliminated. The method is very useful in identifying critical process steps which determine the electrical performance of the devices and circuits

Published in:

IEEE Transactions on Electron Devices  (Volume:40 ,  Issue: 5 )