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A 6-ns 1-Mb CMOS SRAM with latched sense amplifier

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7 Author(s)
Seki, T. ; Fujitsu VLSI Ltd., Aichi, Japan ; Itoh, E. ; Furukawa, C. ; Maeno, I.
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A 1-Mb (256 K×4) CMOS SRAM with 6-ns access time is described. The SRAM, having a cell size of 3.8 μm×7.2 μm and a die size of 6.09 mm×12.94 mm, is fabricated by using 0.5-μm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new NMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle

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Solid-State Circuits, IEEE Journal of  (Volume:28 ,  Issue: 4 )